In a DRAM (Dynamic Random Access Memory), there is a sustained demand for raising the operation frequency and lowering the power supply voltage. For example, the specifications required of the DDR (Double Data Rate) 2-800 standardized by the JEDEC (Joint Electron Device Engineering Council) are for a bus clock of 400 MHz and a power supply voltage of 1.8V. In contrast thereto, the specifications required of DDR3-1600, which is more advanced in generation, are for a bus clock of 800 MHz and a power supply voltage of 1.5V. To wit, in a DRAM, both a high operation frequency and a low power supply voltage are required in combination.
The background for such demand for realization of the speedup of the operation frequency and reduction in the power supply voltage is the need to remove difficulties accompanying the speedup of the operation of both the CPU (Central Processing Unit) and the memory bus. Moreover, if the speed of the memory bus is increased, the charge/discharge current for the memory bus is also increased, with the result that a need is felt for reducing the power supply voltage.
In JP Patent Kokai JP-A-2002-117673 (Patent Literature 1), there is disclosed a circuit that pre-charges a main input/output line MIO arranged between the write amplifier and the sense amplifier.